Although it missed the cell phone era, but now the server and AI era, these two semiconductor "veterans "There is a vast place to play. In order to meet the needs of the terminal, they are also in their own chip design and manufacturing on each of the tricks. For example, Chiplet is becoming their next battlefield. After AMD, the pioneer in this field, Intel also announced the launch of Meteor Lake (Figure 1), a Chiplet-based product, at the Intel Innovation event recently. The architecture of Meteor Lake is described as combining 5 types of tiles: 4 types of tiles (CPU/IO/Graphics/SoC) and the base tile that sits underneath all of them, and with this chip, we are officially witnessing Intel's entry into the full Chiplet era.

    AMD and Intel, too, are once again meeting on the same battlefield.Chiplets are small, modular chips that combine to form complete systems-on-chips (SoCs). They improve performance, reduce power consumption and increase design flexibility. The concept has been around for decades, and back in May 2007, DARPA also launched Chiplet, the COSMOS program for heterogeneous heterogeneous systems, followed by the CHIPS program for Chiplet modular computers. Recently, however, Chiplet has gained attention in addressing the challenge of shrinking the size of traditional monolithic ICs. This is the result of a compromise between the current bottlenecks in the development of the chip manufacturing industry and the contradictions between the end point's demand for chip performance.

     From the chip called "Ponte Vecchio" we can see that Intel has taken full advantage of the advantages of the small chip. As shown in the picture, Ponte Vecchio's overall tile area than the "Sapphire Rapids" to be a little smaller (Sapphire Rapids is 400 square millimeters x 4, that is, 1,600 square millimeters. Ponte Vecchi less than a total of 1, 300 square millimeters), but there is a total of 1,300 square millimeters. 300 sq mm), but there are actually 16 tiles. it consists of a compute tile, 8 Rambo cache tiles, 8 HBM2e I/F tiles, and 2 Xe-Linktiles (there are also a lot of HBM base tiles and controllers, and there are 8 HBMs. but let's exclude them from the count).

      The base tile is quite large, but simply connects the alignments, integrates the HBM controllers, etc., and the process is Intel 7. The compute block size is less than 100 square millimeters because of the use of the TSMC N5. the Rambo Cache still uses Intel The Rambo Cache is still Intel 7, but by the time it gets to the HBM2e SerDes it is TSMC N7. By separating the functional blocks we were able to improve validation and yields, and can now use the best process for each block. Because it uses both EMIB and Foveros package connectivity, it meets 1 and 2 of the Chiplet benefits mentioned above, although it deviates from the chiplet specified by UCIe. in addition to the full Intel Datacenter GPU Max 1550, the lineup includes the half-size Datacenter GPU Max 1100, which meets 3 and 4 of the benefits mentioned above, but given the current state of the industry, it's a good idea to consider a half-size Datacenter GPU Max 1550. In addition to the full Intel Datacenter GPU Max 1550, the line also includes the half-size Datacenter GPU Max 1100, which meets the benefits of 3 and 4, but given that this is not a requirement at this point in time, Ponte Vecchio can be said to be "the product that utilizes the chiplet idea correctly.

      Admittedly, physically it's a chiplet consisting of four tiles, but each tile has all the functionality of a CPU core, a memory controller, a PCIe/CXL, a UPI, and gas pedals, and the tiles measure 400 square millimeters. Also, because we arranged the four tiles in this shape, we had to prepare two mirror-symmetric tiles, so this does not fit the 1 to 3 advantage talked about above. A sample of the successor, Emerald Rapids, was shown at the DCAI Investor Webinar in March of this year (2023) (Fig. 6), but this time it was not necessary to prepare two types of tiles, but the size of the tiles was increased to almost the photomask limit (the chip-size limit), and Advantages 1, 2, and 3 were still completely ignored.